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TLE6288R smart 6 channel peak & hold switch data sheet, rev. 2.5, oct. 2010 automotive power
data sheet 2 rev. 2.5, 2010-10-11 TLE6288R table of contents table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 gerneral functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1.1 output stage control: parallel control and spi control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1.2 current regulator: peak current control with fixed off-ti me . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3.1 parallel diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3.2 electrical characteristics: diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 electrical characteristics: spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 spi diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4 spi commands, values and parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5 spi commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.6 bit assignment and default settings for internal logic registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.7 spi timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 electrical characteristics input / output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 power supply, reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 power outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3 digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4 digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.1 z thjc diagram junction - case for single channel operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.2 thermal application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3 overload/low inductance load detection in current regul ation mode . . . . . . . . . . . . . . . . . . . . . . . 29 8 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table of contents
data sheet 3 rev. 2.5, 2010-10-11 type package TLE6288R pg-dso-36-54 TLE6288R features ? 3 channel high side with adju stable peak & hold current control ? 3 channel high/low side configurable ? protection ? overcurrent (current limitation) ? overtemperature ? overvoltage (active clamping) ? diagnosis ? overcurrent ? overtemperature ? open load (off-state) ? short to ground (off-state, lowside configuration) ?short to v b (off-state, highside configuration) ? interface and control ? 16-bit serial peripheral interface (2 bit/ch) ? device programming via spi ? separate diagnosis output for each ch (diag1 to 6) ? general fault flag + overtemperature flag ? direct parallel control of all channels ? general enable signal to control all channels simultaneously ? low quiescent current ? compatible with 3.3 v and 5 v microcontrollers ? e lectro s tatic d ischarge (esd) protection of all pins ? green product (rohs compliant) ? aec qualified application ? peak & hold loads (valves, coils) ? solenoids, relays and resistive loads ? fast protected highside switching (pwm up to > 10 khz) general description the TLE6288R is a 6-channel (150 m ) smart multichannel switch in smart power technology. the ic has embedded protection, diagnosis and configurable functi ons. channels 1-3 are highside channels with integrated charge pump and can be programmed individually to do autonomous peak and hold current regulation with pwm. channel 4-6 (also with integrated charge pump) can be confi gured to work as highside switch or lowside switch. this ic can be used to drive standard automotive load s in highside or lowside applications with switching frequencies up to 10 khz. in addition the tle62 88r can be used to drive autonomously up to 3 inductive peak & hold (valves, coils) loads with programmable peak and hold current values. table 1 product summary parameter symbol values unit logic supply voltage v cc 4.5 ? 5.5 v on resistance r ds(on)1-6 0.15 typ. @ 25 c lowside clamping voltage v cll(max) +55 v highside clamping voltage v clh(max) -19 v peak current range i pk 1.2 ? 3.6 a hold curr ent range i hd 0.7 ? 2 a peak time range i p 0 ? 3.6 ms fixed off time range i fo 100 ? 400 s
TLE6288R block diagram data sheet 4 rev. 2.5, 2010-10-11 1 block diagram figure 1 block diagram charge pump vcp gnd fsin channel 3 highside 300 m peak&hold channel 2 highside 300 m peak&hold channel 1 highside 300 m peak&hold channel 4 highside/ lowside 300 m channel 5 highside/ lowside 300 m channel 6 highside/ lowside 300 m vb vcc dout 3 / vb sout 3 sout 2 sout 1 dout 4 sout 4 dout 5 sout 5 dout 6 sout 6 spi sclk cs si so logic driver diagnosis in 1 diag 1 in 2 in 3 in 4 in 5 diag 5 in 6 diag 6 overtemp. reset vdo clkprog fault . . vcc vcc . vcc . . vcc . . . . . . . gnd gnd dout 2 dout 1
data sheet 5 rev. 2.5, 2010-10-11 TLE6288R pin configuration 2 pin configuration 2.1 pin assignment figure 2 pin configuration pg-dso-36-54 2.2 pin definitions and functions pin symbol function 1 sout4 source output ch 4 (high/low side) 2 dout4 drain output ch 4 (high/low side) 3 dout1 drain output ch 1 (high side) 4 sout1 source output ch 1 (high side) 5 in4 control input channel 4 6 in1 control input channel 1 7 diag1 diagnostic output ch 1 8 diag2 diagnostic output ch 2 9 diag3 diagnostic output ch 3 10 diag4 diagnostic output ch 4 11 diag5 diagnostic output ch 5 12 diag6/overtemp diagnostic output ch 6 / overtemp 13 in2 control input channel 2 14 in5 control input channel 5 15 sout2 source output ch 2 (high side) 16 dout2 drain output ch 2 (high side)
TLE6288R pin configuration data sheet 6 rev. 2.5, 2010-10-11 2.3 pin description 17 dout5 drain output ch 5 (high/low side) 18 sout5 source output ch 5 (high/low side) 19 sout3 source output ch 3 (high side) 20 dout3 drain output ch 3 (high side) 21 vcp charge pump capacitor pin 22 fsin all channels enable/disable 23 gnd logic ground 24 fault general fault flag 25 in3 control input channel 3 26 in6 control input channel 6 27 reset reset pin (+ standby mode) 28 v cc logic supply voltage (5 v) 29 v do supply pin for digital outputs 30 so spi serial data output 31 clkprog program pin of spi clock 32 sclk spi serial clock 33 cs spi chip select 34 si spi serial data input 35 dout6 drain output ch 6 (high/low side) 36 sout6 source output ch 6 (high/low side) symbol description dout1-3 drain of the 3 highside chan nels. these pins must always be con nected to the same power (battery) supply line ( v b ). sout1-3 source of the 3 highside channels. outputs of the highside channels where the load is connected. dout4-6 drain pins of the 3 configurable channels. in highside configuration they must be connected to the same voltage as dout1-3. in lows ide configuration they are the output pins and connected to the load. sout4-6 source of the 3 configurable channels. in high side configuration they are the outputs and connected to the load. in lowside configuration they must be connected with gnd. in1-6 parallel input pins for the 6 power outputs. these pins have an internal pull-down structure. gnd logic ground pin, the heat slug has to be connected to this potential. fsin disable pin. if the fsin pin is in a logic low state, it switches all outputs off. the pin has an internal pull-up structure. reset reset pin. when the reset is low all channels are o ff, the internal biasing is deactivated, all internal registers are cleared and the supply-current consum ption is reduced (standby mode). the pin has an internal pull-up structure. fault general fault pin. there is a general fault pin (o pen drain) which shows a high to low transition as soon as an error is latched into the diagnosis regist er. when the diagnosis register is cleared this flag is also reset (high ohmic). this fault indication can be used to generate a c interrupt. pin symbol function
data sheet 7 rev. 2.5, 2010-10-11 TLE6288R pin configuration for more details about the spi see chapter 5 . clkprog programming pin for the spi clock signal. this pin can be used to configure the clock signal input of the spi. in low state the spi will read data at the rising clock edge an d write data at the falling clock edge. in high state the spi will read data at the falling cloc k edge and write data at the rising clock edge. the pin has an internal pull-down structure. diag1-5 parallel diagnostic pins (push-pull) change stat e according to the input signal of the corresponding channel. for further details refer to chapter 4.3.1 diag6/ overtemp vcp pin to connect the external capacitor of the inte grated charge pump. connec t a ceramic capacitor with 47 nf between this pin and dout3 ( v b ). v do supply pin of the push-pull digital output drivers. th is pin can be used to vary the high-state output voltage of the so pin and the diag1-6 pins. v cc logic supply pin. this pin is used to supply the integrated circuitry. cs chip select of the spi (active low) so signal output of the s erial p eripheral i nterface si signal input of the s erial p eripheral i nterface. the pin has an internal pull-down structure. sclk clock input of the s erial p eripheral i nterface. the pin has an internal pull-up structure (if clkprog = l) or an pull-down structure (if clkprog = h). symbol description
TLE6288R general product characteristics data sheet 8 rev. 2.5, 2010-10-11 3 general product characteristics 3.1 absolute maximum ratings attention: stresses above the ones listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings 1) t j = -40 ? c to +150 ? c; all voltages with resp ect to ground, positive current flowing into pin (unless otherwise specified) 1) not subject to production test, specified by design. pos. parameter symbol limit values unit pin / conditions min. max. voltages 3.1.1 power supply voltage 1 static dynamic: 1 min. 25 c dynamic: test cond. see figure 3 v b v b v b -0.3 ? ? 20 24 40 vdout1-3 dout1-3 2) dout1-3 2) 2) as long as max. junction temperature t j is not exceeded. 3.1.2 power supply voltage 2 v cc v do -0.3 7 v vcc vdo 3.1.3 continuous drain source voltage (lowside configuration) v dsl ? 40 v dout - sout (channel 4 to 6) continuous source voltage (highside configuration) v sh -9 v b v sout - gnd (channel 4 to 6) 3.1.4 input voltage v in -0.3 v cc + 0.3 v in1-6, reset, fsin, cs, sclk, si, clkprog 3.1.5 output voltage v out -0.3 v cc + 0.3 v fault diag1-6 so 3.1.6 output voltage v cp ? v b + 10 v vcp; no voltage must be applied currents 3.1.7 reverse current (1 ms) i rev -4 ? a between dout and sout; channel 4 to 6 temperatures 3.1.8 operating temperature t j -40 +150 c? 3.1.9 storage temperature t stg -55 +150 c? esd susceptibility 3.1.10 esd (human body model) c = 100 pf, r = 1.5 k applied to all te rminals 3 times v esdb ?2000v? 3.1.11 esd (machine model) c = 200 pf, r = 0 applied to all te rminals 3 times v esdm ?250v?
data sheet 9 rev. 2.5, 2010-10-11 TLE6288R general product characteristics attention: integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault condition s are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. figure 3 test condition 3.2 thermal resistance pos. parameter symbol limit values unit conditions min. typ. max. 3.2.1 ? 3.2.2 junction to case 1) 1) not subject to production test, specified by design. r thjc 1k/w 2) 2) channel 1-6 continously turned on, 0.8w power dissipation per channel 3.2.3 junction to ambient 1) r thja 15.5 k/w 2) 3) 3) specified r thja value is according to jedec jesd51-2,-5,-7 at na tural convection on fr4 2s2p board ; the product (chip+package) was simulated on a 76.2 x 114.3 x 1. 5 mm board with 2 inner copper layers (2 x 70 m cu, 2 x 35 m cu). where applicable a thermal via array under the ex posed pad contacted the first inner copper layer. further informations can be found in chapter 7.2 12v 40v 10 times (once/ 30sec) 160ms 350ms
TLE6288R description data sheet 10 rev. 2.5, 2010-10-11 4 description 4.1 general functional description channel 1 to 3 ? high side configuration with charge pump ? on / off current control ? peak & hold current control with fixed off time, values adjustable by spi ? type of current control can be selected by spi ? peak current,peak time, hold current and off-time can be selected by spi to set average and ripple current for a given load (refer to figure 6 ) channel 4 to 6 ? configurable as either high or low side switch (by spi) ? on / off operation 4.1.1 output stage control: para llel control and spi control a boolean operation (either and or or) is performed on each of the parallel inputs in 1 ? 6 and respective spi data bits, in order to determine the states of the resp ective outputs. the type of boolean operation performed is programmed via the serial interface. both, parallel in puts and respective spi databits are high active. figure 4 serial input bits 6-11 of command ?channels on/off? each output is independently controlled by an output latch and a common reset line fsin, which disables all outputs. a logic high input ?data bit? turns the respective output channel on , a logic low ?data bit? turns it off. table 2 truth table parallel input spi bit output or output and 00offoff 0 1 on off 1 0 on off 1 1 on on or and output driver in 1?6 serial input bits 6 -11 of command ?channels on / off ?
data sheet 11 rev. 2.5, 2010-10-11 TLE6288R description 4.1.2 current regulator: peak curre nt control with fixed off-time ? hold only: when the channel is turned on externally (spi or parallel input) the current rises to the programmed hold current level. then the channel is internally turned off and a timer is started for a fixed off-time (e.g. 200 s). after this time the channel is in ternally turned on again until the hold current level is reached again and so on. this regulation works automatically until the channel is turned of externally. ? peak and hold mode wi th minimum peak time: when the channel is turned on the current rises to the programmed peak current level. then the channel is intern ally turned off, the current regulator changes to hold current values and a timer is started fo r a constant off-time. after this time the channel is internally turned on again until the hold current value is reached and then again turned off for the fixed off time. this regulation works automatically until the chan nel is turned of externally. ? peak and hold mode with programmed peak time: when the channel is turned on the current rises to the programmed peak current level. then the channel is intern ally turned off and a timer is started for a fixed off- time. after this time the channel is in ternally turned on again until the peak current value is reached and then again turned off. this works until the programmed peak time is over. then the current regulator changes to hold current values and works as described under ?hold only?. peak current, peak time, hold current and fixed off-time can be set via spi. to avoid regulation disturbances by current transients during switching (e.g. caused by esd capacitors at the outputs) the current regulator has a ?leading edge blanking? of typical 20 s in all three regu lation modes. after turning on the dmos (internally or externally) the curr ent regulation circuit is deactivated for the first 20 s. this guarantees that switching of the dmos itself or charging of small capacito rs at the output (e.g. esd) is not disturbing the current regulation. to detect shorted loads or low inductance loads in all three regulation modes a timer is started when a channel is turned on ( t li ). if the first rising edge of the load current reaches the programmed current level (peak or hold current depending on the configured current control mode) within this time a overload fault is reported (see chapter 7.3 ). figure 5 simplified functional block diagram
TLE6288R description data sheet 12 rev. 2.5, 2010-10-11 figure 6 current forms of the different current control modes of channel 1-3 peak and hold with set peak time hold only peak & hold with min. peak time i hd i hd i pk i pk t p t fo no regulation current defined only by load input signal i hd t fo t fo t fo
data sheet 13 rev. 2.5, 2010-10-11 TLE6288R description 4.2 protection the TLE6288R has integrated protection functions 1) for overload and short circuit (active current limitation), overtemperature, esd at all pins and overvo ltage at the power outputs (zener clamping). overtemperature behavior each channel has an overtemperature sensor and is individually protected against overtemperature. as soon as overtemperature occurs the channel is immedi ately turned off. in this ca se there are two different behaviors of the affected channel that can be selected by spi (for all channels generally): autorestart: as long as the input signals of the channel remains on (e.g. parallel input high) the channel turns automatically on again after cooling down. latching: after overtemperature shutdown the channel stays off until the this overtemperature latch is reset by a new l h transition of the input signal. note: these overtemperature sensors of the channels are only active if the channel is turned on. an additional overtemperature sensor is located in t he logic of the device. it monitors permanently the ic temperature. as soon as the ic temp erature reaches a s pecified level an overtemper ature fault will be indicated. 1) integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions ar e not designed for continuous repetitive operation.
TLE6288R description data sheet 14 rev. 2.5, 2010-10-11 4.3 diagnostic the TLE6288R has a parallel di agnosis via 6 output pind (diag1 - diag6) and a serial diagnos is functionallity via spi. 4.3.1 parallel di agnostic functions parallel diagnostic pins (push-pull) change state accordin g to the input signal of the corresponding channel. as soon as an error occurs at the corresponding channel (overload and overtemperature is detected in on state and open load/switch bypass in off state) th e diag output shows the inverted input signal. an fault is detected only if it lasts for longer than the fault filter time. th e fault information is not latched in a register. if diag6 is configured as overtemperature flag: this is a general fault pin which shows a high to low transition as soon as an overtemperature error occurs for any o ne of the six channels (for longer than the fault filter time) or the ic logic. this fault indication can be used to differ between overload and overtemperature errors in one of the six channels or to detect a general ic overtemperature. 4.3.2 electrical characteris tics: diagnostic functions electrical characterist ics: diagnostic functions v cc = 4.5 v to 5.5 v, t j = -40 ? c to +150 ? c, v b = 6 v to 16 v, reset = h, v do = v cc , all voltages with respect to ground, positive current flowing in to pin (unless otherwise specified) pos. parameter symbol limit values unit pin/ comment conditions min. typ. max. 4.3.1 open load detection voltage v ds(ol) ?5.5?v? lowside configuration, v b = 12 v 4.3.2 open load detection voltage v ds(ol) ? 4.5 ? v ? highside configuration, v b = 12 v 4.3.3 output open load diagnosis current i d(ol) -500 -100 -20 a? v b = v out = 12 v 4.3.4 fault filter time t f(fault) 50 100 200 s? ? 4.3.5 switch bypass detection current i d(sb) ??250 a? ? 4.3.6 overload detection threshold (channel 1 to 3) i dd(lim1-3) 4 ? 6 a ? no regulation mode 4.3.7 overload / low inductance load detection time (channel 1 to 3) t li ?? t fo ssee chapter 7.3 current control mode 4.3.8 overload detection threshold (channel 4 to 6) i dd(lim 4-6) 3?6a? ?
data sheet 15 rev. 2.5, 2010-10-11 TLE6288R spi 5spi the spi is a s erial p eripheral i nterface with 4 digital pins and a 16-bit sh ift register. the spi is used to configure and program the device, turn on and off channels and to read detailed diagnostic information. figure 7 serial peripheral interface 5.1 spi signal description cs - chip select. the system microcontr oller selects the TLE6288R by means of the cs pi n. whenever the pin is in a logic low state, data can be transferred from the c and from the TLE6288R to the c. ? cs = h: any signals at the sclk and si pins are ignored and so is forced into a high impedance state. ? cs = h l: ? diagnostic information is transferred from the diagnosis register into the spi shift register ? serial input data can be clocked into the spi shift register from then on ? so changes from high impedance state to logic high or low state corresponding to the so bits figure 8 ? cs = l: spi is working like a shift register. with each clock signal th e state of the si is read into the spi shift- register and one diagnosis bit is written out of so. ? cs = l h: ? transfer of si bits from spi shift regi ster into the internal logic registers ? reset of diagnosis regist er if sent command was valid to avoid any false clocking the serial clock input pin sclk should be logic high state (if clkprog = l; low state if clkprog = h) during high to low transition of cs . sclk - serial clock. the serial clock pin clocks the internal spi shift register of the TLE6288R. the serial input (si) accepts data into the input spi shift register on the rising edge of sclk (if clkprog = l; falling edge if clkprog = h) while the serial output (so) shifts diagnostic inform ation out of the spi shi ft register on the falling spi cs sclk si so internal logic registers diagnosis register 16 bit spi shift register si so cs cs msb msb lsb lsb serial input data msb first serial output (diagnosis) msb first
TLE6288R spi data sheet 16 rev. 2.5, 2010-10-11 edge (if clkprog = l; rising edge if clkprog = h) of serial clock. it is essential that the sclk pin is in a logic high state (if clkprog = l; low state if cl kprog = h) whenever chip select cs makes any transition. si - serial input. serial data bits are shifted in at this pi n, the most significant bit (m sb) first. si information is read in on the rising edge of sclk (if clkprog = l; falling edge if clkpro g = h). input data is la tched in the spi shift register and then transferred to th e internal registers of the logic. the input data consists of 16 bits, made up of 4 control bits and 12 data bits . the control word is used to program the device, to operate it in a certain mode as well as providing diagnostic information (see chapter 5.5 ). so - serial output. diagnostic data bits are shifted out serially at this pin, the most significant bit (msb) first. so is in a high impedance state until the cs pin goes to a logic lo w state. new diagnostic data will appear at the so pin following the falling edge of sclk (if clkprog = l; rising edge if clkprog = h). 5.2 electrical charact eristics: spi timing electrical characteristics: spi timing v cc = 4.5 v to 5.5 v, t j = -40 ? c to +150 ? c, v b = 6 v to 16 v, reset = h, v do = v cc , all voltages with respect to ground, positive current flowing in to pin (unless otherwise specified) pos. parameter symbol li mit values unit pin/ comment conditions min. typ. max. 5.2.1 serial clock frequency (depending on so load) f sclk dc ? 5 mhz ? ? 5.2.2 serial clock period (1/ f sclk ) t p(sclk) 200??ns? ? 5.2.3 serial clock high time t sclkh 50??ns? ? 5.2.4 serial clock low time t sclkl 50??ns? ? 5.2.5 enable lead time (falling edge of cs to falling edge of sclk) t leadl 200??ns? clkprog = l enable lead time (falling edge of cs to rising edge of sclk) t leadh 200??ns? clkprog = h 5.2.6 enable lag time (rising edge of sclk to rising edge of cs ) t lagl 200??ns? clkprog = l enable lag time (falling edge of sclk to rising edge of cs ) t lagh 200??ns? clkprog = h 5.2.7 data setup time (required time si to rising of sclk) t sul 20??ns? clkprog = l data setup time (required time si to falling of sclk) t suh 20??ns? clkprog = h 5.2.8 data hold time (rising edge of sclk to si) t hl 20??ns? clkprog = l data hold time (falling edge of sclk to si) t hh 20??ns? clkprog = h 5.2.9 disable time 1) t dis ??200ns? ?
data sheet 17 rev. 2.5, 2010-10-11 TLE6288R spi 5.3 spi diagnostics as soon as a fault occurs for longer than the fault filter time, the fault information is latched into the diagnosis register (and the fault pin will change from high to low state). a new error on the same channel will overwrite the old error report. serial data out pin (so) is in a high impedance state when cs is high. if cs receives a low signal, all diagnosis bits can be shifted out serially . if the sent command was valid (see note in chapter 5.5 ) the rising edge of cs will reset the diagnosis registers (e xcept the channel ot flag) and rest art the fault filter time. in case of an invalid command the device will igno re the data bits and the diagnosis r egister will not be reset at the rising cs edge. figure 9 two bits per channel diagnostic fe edback plus two overtemperature flags for full diagnosis there are two diagnostic bits per channel configured as shown in figure 9 . diagnosis bit 0 and bit 1 are always set to 1. 5.2.10 transfer delay time 2) (cs high time between two accesses) t dt 200??ns? ? 5.2.11 data valid time 1) c l = 50 pf to 100 pf c l = 220 pf t valid ? ? ? ? 120 150 ns ? ? 1) not subject to production test, specified by design. 2) to get the correct diagnostic information, the transfer delay time has to be extended to the maximum fault filter time t f(fault)max = 200 s. electrical characteristics: spi timing (cont?d) v cc = 4.5 v to 5.5 v, t j = -40 ? c to +150 ? c, v b = 6 v to 16 v, reset = h, v do = v cc , all voltages with respect to ground, positive current flowing in to pin (unless otherwise specified) pos. parameter symbol li mit values unit pin/ comment conditions min. typ. max. diagnostic serial data out so hh normal function hl overload, shorted load or overtemperature lh open load ll switch bypassed ch.6 ch.5 ch.4 ch.3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msb ch.2 ch.1 lsb channel overtem- perature flag ic overtem- perature flag bit0 and bit1 is always 1
TLE6288R spi data sheet 18 rev. 2.5, 2010-10-11 normal function: the bit combination hh indicates that there is no fault condition, i.e. normal function. overload, shorted load or overtemperature: hl is set when the current limitatio n gets active, i.e. there is a overload, short to supply or overtemperature condit ion. the second reason for this bit combination is overtemperature of the corresponding channel. in current regulation mode hl is also set if the load current reaches the programmed current value in a time shorter than the fixed off time ( t fo ). this detection is only performed at the fi rst rising load current edge after a channel is turned on (for channel 1 to 3). see chapter 7.3 . open load: lh is set when open load is detected (in off state of the channel). switch bypassed: ? short to gnd: in lowside configurat ion ll is set when this condition is detected. ? short to battery: in highside configuration ll is se t when this condition is detected. channel overtemperature flag: in case of overtemperature in any output channel in on state the overtemperature flag in the spi diagnosis register is set (change bit 3 from 0 to 1). this bit can be used to distinguish between overload and overte mperature (both hl combination) and is reset by switching off/on the affected channel. in addition the diag6 / overtemp pin is se t low (if configured as overtemp flag). ic overtemperature flag: when the ic logic temperature exceeds typ. 170 c the non-latching ic overtemperature flag will be set in the spi diag nosis register (change bit 2 from 0 to 1). in addition the diag6 / overtemp pin is se t low (if configured as overtemp. flag). 5.4 spi commands, values and parameters the 16-bit spi is used to program different ic functions and values, turn on and off the channels and to get detailed diagnosis information. therefore 4 comm and bits and 12 data bits are used. figure 10 si so cs 4 bits 12 bits command data diagnosis ( ch. 1 to 6) + 2 temp. flags si command : 4 command bits program the operation mode of channels 1 to 6. 12 data bits configure the device and give the input information (on or off) for channel 1 to 6. so diagnosis 16 bit diagnosis information (two bit per channel) of channels 1 to 6 plus two overtemperature flags
data sheet 19 rev. 2.5, 2010-10-11 TLE6288R spi the following parameters and functional behavior can be programmed by spi: ? current regulation mode (mode): for each of the 3 highside channels individually the operation mode can be set. ? ?no current regulation? ? current regulation ?hold only? ? current regulation ?peak & hold with minimum peak time? ? current regulation ?peak & hold with programmed peak time? ? peak current ( i pk ): for each of the 3 highside channels individually the peak current value for p&h current regulation can be programmed. the current range is 1.2 a to 3.6 a. ? fixed off time of the current regulator ( t fo ): for each of the 3 highside channe ls (ch1 to ch3) individually the fixed off time for all modes with current regulation can be programmed from 100 s to 400 s. ? hold current ( i hd ): for each of the 3 highside cha nnels (ch1 to ch3) individually the hold current value for p&h and hold only current regulation can be programmed. the current range is 0.7 a to 2.0 a. ? peak time ( t p ): for each of the 3 highside channels (ch1 to ch3) individually the pe ak time value for p&h current regulation can be programmed. the time range is 0.8 ms to 3.6 ms. ? highside/lowside configuration (h/l): each of the 3 configurable channels (ch4 to ch6) can be programmed for use as highside switch or lowside switch. ? open load and switch bypassed detection activated or deactivated (ol+sb): for each of the 3 configurable channels (ch4 to ch6) the open load and switch bypassed diagnosis can be deactivated. in lowside configuration the open load and the short to gnd detection can be deactivated, in highside configuration the open load a nd short to battery detection. ? boolean operation (or/and): for all channels generally the bool ean operation of the parallel input signal and the spi bit of the corresponding channel can be defined. ? overtemperature behavior (r/l): the overtemperature behavior of the channels can be programmed by spi. autorestart or latching overtemperature shutdown can be selected (for all channels the same behavior). ? diag6 or overtemperature flag (d/f): with this spi bit the function of the diag6 / overtemp pin is defined. this output can work as diagnosis output of channel 6 or as overtemperature flag. 5.5 spi commands table 3 command table command msb14131211 10 9 8 7 6 5 4 3 2 1 lsb set all to default 1 000xx xx xx x xx xxx config. regulator 1 1 0 0 1 mode i pk t fo i hd t p x config. regulator 2 1 0 1 0 mode i pk t fo i hd t p x config. regulator 3 1 0 1 1 mode i pk t fo i hd t p x config. ch1 - ch6 1 1 0 0 ch6 h/l ch6 ol+ sb ch5 h/l ch5 ol+ sb ch4 h/l ch4 ol+ sb all or/ and all r/l diag 6d/f xxx channels on/off 1 1 0 1 ch6 ch5 ch4 ch3 ch2 ch1 x x x x x x diagnosis only 1 1 1 1 x x x x x x x x x x x x
TLE6288R spi data sheet 20 rev. 2.5, 2010-10-11 legend of spi command table ? mode: operation mode of the current regulator: ? no regulation ? hold only ? peak & hold with minimum peak time ? peak & hold with programmed peak time ? i pk : peak current values 1.2 a ? 3.6 a ? i hd : hold current values 0.7 a ? 2 a ? t p : peak time value 0.8 ms ? 3.6 ms ? t fo : fixed off time value 100 s ? 400 s ? h/l: channel 4 to 6 in highsi de or lowside configuration ? ol+sb: open load detection and switch bypa ssed detection activated or deactivated ? or/and: boolean operation (paralle l input and corresponding spi bit) ? r/l: autorestart or latching overtemperature behaviour ? d/f: diag6/overtemp pin set as diagnosis output of channel 6 or as overtemperature flag ? ch1-ch6: on/off information of the output drivers (high active) command description config. regulator 1-3: with this command the values for the curren t regulation and the functional mode of the channel is written into the internal logic registers. config. ch1 to ch6: this command writes the configuration data of the 3 configurable channels (4-6) and sets the boolean operation and overtemperature behavior of all channels. it also sets the diag6/overtemp. pin to diagnosis of channel 6 or overtemperature flag. set all to default: this command sets all internal logic registers back to default settings. diagnosis only: when this command is sent the 12 data bits ar e ignored. the internal logic registers are not changed. channels on/off: with this command the spi bits for the on /off information of the 6 channels are set. note: specified control words (valid commands) are executed and the diagnosis register is reset after the rising cs edge. not specified control words are not exec uted (cause no function) and the di agnosis register is not reset after the cs = l h signal.
data sheet 21 rev. 2.5, 2010-10-11 TLE6288R spi 5.6 bit assignment and default sett ings for internal logic registers default settings are in bold print . mode 00 no current regulation 01 hold only 10 p&h minimum peak time 11 p&h with programmed times peak current ( i pk ) 1.2 a 1.8 a 2.4 a 3.6 a 2 bits 00 01 10 11 hold current ( i hd ) 0.7 a 1.0 a 1.4 a 2.0 a 2 bits 00 01 10 11 fixed off time ( t fo ) 100 s 200 s 300 s 400 s 2 bits 00 01 10 11 peak time ( t p ) 0.8 ms 1.2 ms 1.6 ms 2.0 ms 2.4 ms 2.8 ms 3.2 ms 3.6 ms 3 bits 000 001 010 011 100 101 110 111 boolean operation or and 1 bit 0 1 overtemp. behavior restart latch 1 bit 0 1 diag6 / overtemp diag6 overtemp. flag 1 bit 0 1 highside / lowside highside lowside 1 bit 0 1 open load & sb (4-6) yes no 1 bit 0 1 channels on / off off on 1 bit 0 1
TLE6288R spi data sheet 22 rev. 2.5, 2010-10-11 5.7 spi timing diagrams figure 11 input timing diagram (clkprog = l) figure 12 so valid time waveforms and enable and disable time waveforms (clkprog = l) figure 13 serial interface t leadl t sckh 0.2v cc t la gl t hl t sckl 0.2 v cc t sul 0.7v cc 0.2v cc cs sclk si 0.7v cc t dt 0.7v cc t vali d sclk cs so t dis 0.2 v cc so 0.2 v cc 0.7 v cc 0.2 v cc so 0.7 v cc 0.2 v cc 4 control bit 12 data bit c o n t r o l word 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cs sclk si so msb lsb
data sheet 23 rev. 2.5, 2010-10-11 TLE6288R spi figure 14 input timing diagram (clkprog = h) figure 15 so valid time waveforms and enable and disable time waveforms (clkprog = h) figure 16 serial interface t leadh t sckh 0.2v cc t la gh t hh t sck l 0.2 v cc t suh 0.7v cc 0.2v cc cs sclk si 0.7v cc t dt 0.7v cc t valid sclk cs so t dis 0.2 v cc so 0.7 v cc 0.7 v cc 0.2 v cc so 0.7 v cc 0.2 v cc 4 control bit 12 data bit c o n t r o l word 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cs sclk si so msb lsb
TLE6288R electrical characteristics input / output pins data sheet 24 rev. 2.5, 2010-10-11 6 electrical characteristi cs input / output pins 6.1 power supply, reset 6.2 power outputs electrical characteristics: power supply, reset v cc = 4.5 v to 5.5 v, t j = -40 ? c to +150 ? c, v b = 6 v to 16 v, reset = h, v do = v cc , all voltages with respect to ground, positive current flowing in to pin (unless otherwise specified) pos. parameter symbol li mit values unit pin/ comment conditions min. typ. max. 6.1.1 power supply current 1 i b ? ? 10 ma dout1-3 ch1-ch6: off 6.1.2 power supply current 2 i cc ??10ma v cc ? 6.1.3 power supply current in standby mode i cc + i b ??50 a dout1-3, v cc reset = l 6.1.4 minimum reset duration t reset,min 50 ? ? s? ? 6.1.5 wake-up time after reset t wakeup ??5ms? c cp = 10 nf electrical characteristics: power outputs v cc = 4.5 v to 5.5 v, t j = -40 ? c to +150 ? c, v b = 6 v to 16 v, reset = h, v do = v cc , all voltages with respect to ground, positive current flowing in to pin (unless otherwise specified) pos. parameter symbol limit values unit pin/ comment conditions min. typ. max. 6.2.1 on resistance r ds(on) ??350m doutx - soutx i d = 2.4 a v b = 10 v 6.2.2 forward voltage revers diode v rdf ??2vsoutx - doutx i d = -4 a t j = 150 c 6.2.3 peak current range i pk ? 1.2 ? 3.6 ?a? ? 6.2.4 peak current accuracy i pka ?? 15 20 % % ? t j = 25, 150 c t j = -40 c 6.2.5 hold current range i hd ?0.7 ? 2?a? ? 6.2.6 hold current accuracy i hda ?? 15 20 % % ? t j = 25, 150 c t j = -40 c 6.2.7 peak time range t p ? 0.8 ? 3.6 ?ms? ? 6.2.8 peak time accuracy t pa ?? 20 % ? ? 6.2.9 fixed off time range t fo ? 100 ? 400 ? s? ? 6.2.10 fixed off time accuracy t foa ?? 30 % ? 100 s 6.2.11 fixed off time accuracy t foa ?? 20 % ? 200 s - 400 s 6.2.12 output on delay time1 t don ??10 s? see figure 17 6.2.13 output on rise time1 t r ??10 s? see figure 17
data sheet 25 rev. 2.5, 2010-10-11 TLE6288R electrical characteristics input / output pins 6.3 digital inputs 6.2.14 output off delay time t doff ??20 s ? hs- mode ls- mode see figure 17 6.2.15 output off fall time t f ??10 s? see figure 17 6.2.16 leakage current ? ? ? 10 a ? reset = l 6.2.17 leak current in off (highside configuration) i loff ??-250 asout1-6? 6.2.18 leak current in off (lowside configuration) i loff ??500 adout4-6? 6.2.19 output clamp voltage (highside configuration) v clh -19 -14 -9 v sout1-6 refers to gnd level 6.2.20 output clamp voltage (lowside configuration) v cll 40 ? 55 v dout4-6 refers to gnd level 6.2.21 current limitation (channel 1 to 3) i dlim1-3 4?6a? ? 6.2.22 current limitation (channel 4 to 6) i dlim4-6 3?6a? ? 6.2.23 ic overtemp. warning 1) hysteresis t ot t hys 160 ? ? 10 180 ? c c ?? 1) not subject to production test, specified by design. electrical characteri stics: digital inputs v cc = 4.5 v to 5.5 v, t j = -40 ? c to +150 ? c, v b = 6 v to 16 v, reset = h, v do = v cc , all voltages with respect to ground, positive current flowing in to pin (unless otherwise specified) pos. parameter symbol li mit values unit pin/ comment conditions min. typ. max. 6.3.1 input low voltage v inl ??1vall digit. inputs ? 6.3.2 input high voltage v inh 2??v all digit. inputs ? 6.3.3 input voltage hysteresis v inhys ? 100 ? mv all digit. inputs ? 6.3.4 input pull-down current i pd 20 50 100 ain1-6; clkprog v in = 5 v 6.3.5 input pull-up current i pu -100 -50 -20 areset; fsin v in = gnd electrical characteristics: power outputs (cont?d) v cc = 4.5 v to 5.5 v, t j = -40 ? c to +150 ? c, v b = 6 v to 16 v, reset = h, v do = v cc , all voltages with respect to ground, positive current flowing in to pin (unless otherwise specified) pos. parameter symbol limit values unit pin/ comment conditions min. typ. max.
TLE6288R electrical characteristics input / output pins data sheet 26 rev. 2.5, 2010-10-11 6.4 digital outputs figure 17 turn on/off timings with resistive load 6.3.6 spi input pull-down current i pd 10 20 50 a si, sclk (clkprog = h) v in = 5 v 6.3.7 spi input pull-up current i pu -50 -20 -10 a cs, sclk (clkprog = l) v in = gnd electrical characterist ics: digital outputs v cc = 4.5 v to 5.5 v, t j = -40 ? c to +150 ? c, v b = 6 v to 16 v, reset = h, v do = v cc , all voltages with respect to ground, positive current flowing in to pin (unless otherwise specified) pos. parameter symbol li mit values unit pin/ comment conditions min. typ. max. 6.4.1 so low state output voltage v sol ??0.4vso i sol = 2.5 ma 6.4.2 so high state output voltage v soh v do - 0.4 v ??vso i soh = -2 ma 6.4.3 diag low state output voltage v diagl ??0.4vdiag1-6 i diagl = 50 a 6.4.4 diag high state output voltage v diagh v do - 0.4 v ??vdiag1-6 i diagh = -50 a 6.4.5 fault low output voltage v ol ? ? 0.4 v fault i out = 1 ma 6.4.6 fault output leak current i oh ??1 a fault output: off v (fault) = 5 v electrical characteri stics: digital inputs (cont?d) v cc = 4.5 v to 5.5 v, t j = -40 ? c to +150 ? c, v b = 6 v to 16 v, reset = h, v do = v cc , all voltages with respect to ground, positive current flowing in to pin (unless otherwise specified) pos. parameter symbol li mit values unit pin/ comment conditions min. typ. max. input voltage output voltage (highside configuration) 70% 30% t don t doff t r t f
data sheet 27 rev. 2.5, 2010-10-11 TLE6288R application information 7 application information 7.1 z thjc diagram junction - case for single channel operation figure 18 z thjc diagram ? conditions for figure 18 ? results based on fem simulations ? t case = 125 c ? single channel operation, 0.8w power dissipation 7.2 thermal appli cation information all thermal resistance values in th is document are data from fem (f inite element mode lling). the boundary conditions are chosen according to the jesd51 standa rd. therefore, all values can be viewed as reliable and reproducible. the high effective thermal conductivity test pcb (2s 2p) gives a near best case thermal performance value. compared to the single layer low effective thermal cond uctivity pcb (1s). it should be emphasized that values measured/simulated with these test boards cannot be used to directly predict any particular system application performance. in real applications, the r thja can be influenced by the environment and pcb conditions. thermal vias, application specific multi layer pcbs a nd a direct thermal connection to the ecu metal-case are often used to improve the thermal impedance r thja . 0,01 0,1 1 10 0,000001 0,00001 0,0001 0,001 0,01 0,1 pulse width [s] zth(d, pulse width) [k/w ] 0,5 0,2 0,1 0,05 0,02 0,01 dutycycle d
TLE6288R application information data sheet 28 rev. 2.5, 2010-10-11 figure 19 fe model of the jedec 2s2p pcb figure 20 thermal via layout figure 19 showes the product TLE6288R on the 2s2p board used to specify the typical r thja value in chapter 3.2 . in figure 20 , the thermal via layout acco rding to jesd51-5 is shown.
data sheet 29 rev. 2.5, 2010-10-11 TLE6288R application information 7.3 overload/low inductance load de tection in curren t regulation mode figure 21 load current normal condition i pk / i hd t fo input signal t li load current low-inductance load i pk / i hd t fo t li overload / low inductance load detection load current normal condition i pk / i hd t fo input signal t li load current low-inductance load i pk / i hd t fo t li overload / low inductance load detection
TLE6288R package outlines data sheet 30 rev. 2.5, 2010-10-11 8 package outlines figure 22 pg-dso-36-54 (plastic dual small outline package) green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). bottom view does not include plastic or metal protrusion of 0.15 max. per side 1 18 0.25 ?.1 1.1 36 +0.13 0.25 36x 19 m (heatslug) 15.74 0.65 ?.1 c ab 19 c 3.25 3.5 max. +0.1 0 0.1 ?.1 36 2.8 b 11 ?.15 1) 1.3 5? 0.25 ?? -0.02 +0.07 6.3 14.2 (mold) ?.3 b ?.15 0.25 heatslug 0.95 heatslug ?.1 5.9 3.2 (metal) ?.1 (metal) 13.7 (metal) 10 1 -0.2 index marking (mold) 15.9 1) ?.1 a 1 x 45? 1) gps09181 you can find all of our packages, so rts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . dimensions in mm
data sheet 31 rev. 2.5, 2010-10-11 TLE6288R revision history 9 revision history revision date changes 2.2 2004-03-25 preliminary datasheet TLE6288R vp2.2 2.3 2006-05-03 formal changes, thermal information added, spec. values not changed 2.4 2007-08-08 rohs-compliant version of the TLE6288R page 3: ?aec qualified? and ?rohs? logo added, ?green product (rohs compliant)? and ?aec qualified? statement added to feature list, package names changed to rohs compliant versions, package pictures updated page 30: package names changed to rohs compliant versions, ?green product? description added revision history updated legal disclaimer updated 2.5 2010-10-11 updated package type
edition 2010-10-11 published by infineon technologies ag 81726 munich, germany ? 2010 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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